An antifuse which allows for redundancy swapping, that is, replacing a fail cell with a redundant cell, in a packaged state of a chip, has come to be used in recent years. A capacitance fuse is a sort of antifuse in which a capacitor structure is formed in an antifuse material. With the capacitance fuse, if high voltage is applied across an upper electrode and a lower electrode of a capacitor, a dielectric film between the two electrodes undergoes insulation breakdown so that a conducting path is formed between the two electrodes. The address information on the fail cell may be written even after mounting a chip into a package and may be used for remedying the hold deterioration fail of a memory cell even after the assembly and packaging. The antifuse is ordinarily used for remedying smaller numbers of bits because the chip area increases with increase in the number of antifuses in use. As for a redundancy circuit employing an antifuse, reference is made to Patent Document 1, as an example.
The smaller numbers of fail bits, that can be remedied by the antifuses, are detected based on checked results of the fail information on the tester side. In case the check on the tester side is not possible, the capacitance fuses are connected to all defective products before conducting check for fails.
The on-chip comparison function latches the first bit fail due to its circuit configuration. Thus, in case a semiconductor memory device is equipped with such on-chip comparison function, it is impossible to detect a chip that allows for replacement by an anti-fuse, such as a capacitance fuse.
FIG. 6 is a block diagram showing a typical illustrative configuration of a semiconductor memory device adopting a double data rate (DDR). This conventional semiconductor memory device includes a clock control circuit 4, a control signal generating circuit 3, an address buffer 5, a memory cell array 6, a data control circuit 7, a data-out buffer 8, a data-in buffer 9, a test mode entry circuit 10, an on-chip compare circuit 1 and an on-chip compare latch circuit 2.
The control signal generating circuit 3 receives an address signal 101, a CSB (chip select) signal 102, an RASB (row address strobe) signal 103, a CASB (column address strobe) signal 104, a WEB (write enable) signal 105 and an internal clock signal 122, and outputs a control signal 120. Meanwhile, the upper case letter B affixed to the ends of respective signal names, namely CSB, RASB, CASB and WEB, indicates that the signals are active at a low level (low-active signal).
The control signal 120 is supplied to the address buffer 5, memory cell array 6, data control circuit 7, test mode entry circuit 10 and to the on-chip compare latch circuit 2.
The clock control circuit 4 receives clock signals, namely a CK signal 106 and CKB signal (a complementary signal of CK) 107, and a CKE signal 108, which is a clock enable signal, to generate an internal clock signal 122, which is supplied to the control signal generating circuit 3, memory cell array 6 and to the data control circuit 7.
The test mode entry circuit 10 receives the address signal 101 and control signal 120 to output a PTEST signal 111 and a TCMP1 signal 112.
The address buffer 5 receives the address signal 101, control signal 120 and PTEST signal 111 to output a select signal 121 to the memory cell array 6.
The memory cell array 6 receives the control signal 120, select signal 121 and internal clock signal 122 to output data bus signals DB0 to DB3 (113 to 116). Although FIG. 6 shows four data buses, for simplicity, the number of the data buses is, of course, not restricted to four.
The data control circuit 7 receives the data bus signals DB0 to DB3 (113 to 116), PTEST signal 111, select signal 121, control signal 120 and internal clock signal 122 to output a read/write bus signal 123.
The on-chip compare circuit 1 receives the data bus signals DB0 to DB3 (113 to 116) and an input data signal from an external I/O terminal 119 to output a TFF0B signal 117.
The on-chip compare latch circuit 2 receives the TFF0B signal 117, PTEST signal 111, TCOM signal 112 and the control signal 120 to output a TTRN signal 118.
The data-out buffer 8 receives the read/write bus signal 123, TTRN signal 118, DQS signal 109 and DM signal 110 to output data at the external I/O 119.
The data-in buffer 9 receives data from the I/O 119, while also receiving the DQS signal 109 and DM signal 110 to output data on the read/write bus 123.
The operation of the semiconductor memory device of FIG. 6 will now be described. Initially, the operation of reading/writing data without employing a test mode circuit system (normal operation) will be described.
The address signal 101 is held in the address buffer 5. Based on the select signal 121, held in the address buffer, a word line and a bit line in the memory cell array 6 are selected. For a read operation, memory cell data, selected in this manner, are output to the data buses DB0 to DB3 (113 to 116) and thence to the read/write bus 123 via data control circuit 7. Hence, data is read out from the data-out buffer 8 via external I/O 119.
The operation for writing data entered to the data-in buffer 9 from the I/O 11 occurs in a reverse sequence to that for reading out the data. That is, input data on the read/write bus 123 is supplied via data control circuit 7 to the data buses DB0 to DB3 (113 to 116) and written in selected memory cells in the memory cell array 6.
The operation for the on-chip compare test mode will now be described with reference to FIGS. 6 to 9.
The on-chip compare test mode is one of test modes carried out in a screening process. The read data read from a memory cell in the chip is compared with write data supplied from the external I/O (expected value) and the non-coincidence information (fail information) is latched. After completion of the test, latched data is read out once and checked.
In a large-size parallel tester, such as a TBT(tester burn-in test) equipment used in a screening process, in which there is imposed a limitation on the number of device-side comparators, all-chip test is not completed except if the same test is carried out a preset number of times. Thus, if the device-side comparators are not used during test, the entire chips may be tested simultaneously, so that test time may be reduced to that for only one testing. It is sufficient that testing is carried out in the on-chip comparison test mode and that the latch information for each chip is read only once and for all. This leads to marked reduction in the test time.
The circuit operation of the on-chip comparison test will now be described. FIG. 7 is a diagram showing an illustrative configuration of the on-chip compare circuit 1 of FIG. 6. The on-chip compare circuit includes a four-input EXOR (exclusive-OR) circuit 11, receiving data bus signals DB0 to DB3 (113 to 116) as inputs, a two-input EXOR circuit 12, receiving compare write data and DB3 as inputs, and a NOR circuit 13, receiving outputs of the EXOR circuits 11, 12 as inputs.
A signal line 125, as an output of the EXOR (exclusive-OR) circuit 11, goes LOW only when the entire data of the data bus signals DB0 to DB3 (113 to 116) of the memory cell array information, read out from the memory cell array 6, are coincident with one another. A signal line 126, which is an output of the EXOR 12, goes LOW only when data 124, assumed herein to be DB3, from a sole I/O pin, assumed herein to be I/03, out of write data applied at this time to the I/O 119, and one of the data bus signals DB0 to DB3 (113 to 116), are coincident with each other. The TFF0B signal 117 is output from a NOR circuit 13 which receives the signals 125, 126. That is, the TFF0B signal 117 becomes HIGH only when the data bus signals and the compare write data are all coincident. If any of the data bus signals and the compare write data is non-coincident, the TFF0B signal 117 becomes LOW. The internal fail information becomes data on the TFF0B signal line 117.
FIG. 8 is a diagram showing an illustrative configuration of the on-chip compare latch circuit 2. This on-chip compare latch circuit 2 outputs data as it is on the TFF0B signal line 117 or outputs data which is the latched LOW level information of the TFF0B signal 117 which has indicated a failed state if only once.
The operation of a PDEBL signal 127, an OCCRST signal 128 and an OCOUTB signal 129 of FIG. 8, which are the control signals 120 output from the control signal generating circuit 3 of FIG. 6 and generated with a test mode entry signal, and the PTEST signal 111 and the TCMP1 signal 112, which are test mode signals, output from the test mode entry circuit 10 of FIG. 6, will now be described.
The test mode signal is used for screening and evaluation of the device but is not used on the part of the user of the device. Hence, the test mode signal is entered with a specified timing and address. This entry is made by the test mode entry circuit 10.
The PTEST signal 111 controls the test mode called ‘parallel test mode’. Since bit-by-bit based testing of the memory cell array is time-consuming, plural addresses are compressed and plural items of data are read or written in parallel.
The TCMP1 signal 112 is a test mode signal used for latching and outputting the fail information obtained by on-chip comparison. The TCMP1 signal 112 is used simultaneously with the PTEST signal 111.
The PDBEL signal 127 is a latch gate signal.
The OCCRST signal 128 is a signal for initializing the latch information.
The OCOUTB signal 129 is a signal for enabling the data information to be latched in the on-chip comparison and output to the data-out circuit.
Referring to FIG. 8, the on-chip compare latch circuit 2 is divided into a path which uses as it is, an output signal 130 of a NAND circuit 14 which receives the PTEST signal 111 and TFF0B signal 117, and a path which latches and outputs the first LOW level information of the TFF0B signal 117.
The path which uses the signal 130 as it is, is supplied to the gate of an inverter 15 to output a signal 131. The signal 131 connected to a signal 132 via a transfer gate made up of a P-channel MOS transistor 25 and an N-channel MOS transistor 26. The gate of the P-channel MOS transistor 25 is supplied with the TCMP1 signal 112. The gate of the N-channel MOS transistor 26 is supplied with a signal 196 output from the inverter 24 which inverts the TCMP1 signal 112. An inverter 129 inverts the signal 132 to output a signal 133.
A NAND circuit 23 receives as inputs, the OCOUTB signal 129 and TCMP1 signal 112 to output a signal 140.
A NAND circuit 30 receives the signals 140 and 133 to output a signal 134. An inverter 31 receives and inverts the signal 134 to output the TTRN signal 118.
The path which latches and outputs the first LOW level information (fail information) of the TFF0B signal 117 is connected to a signal 135 via a transfer gate made up of an N-channel transistor 17 and a P-channel transistor 18. The gate of the N-channel transistor 17 is supplied with the PDEBL signal 127, while the gate of the P-channel transistor 18 is supplied with a signal 139 obtained on inverting the PDEBL signal 127 by an inverter 16.
There is provided a latch circuit composed of inverters 20A and 20B. The inverters 20A and 20B operate in such a manner that the signal 135 is supplied to and inverted by the inverter 20A so as to be output as a signal 138, which is supplied to and inverted by the inverter 20B so as to be connected to the signal 135.
The signal 135 is supplied to one input of a NOR circuit 21, which NOR circuit 21 outputs a signal 136. The signal 136 is supplied to one input of a NOR circuit 22, the other input of which receives the OCCRST signal 128. The NOR circuit 22 outputs a signal 137, which is supplied to the other input of the NOR circuit 21.
An N-channel transistor 19 which has a gate supplied with the OCCRST signal 128, is connected between the signal line 135 and the ground.
The signal 136 is connected to the signal 132 via a transfer gate made up by an NMOS transistor 28 and a P-channel MOS transistor 27. The gate of the NMOS transistor 28 is supplied with the TCOM1 signal 112, while the gate of the P-channel MOS transistor 27 is supplied with the signal 196 obtained on inverting the TCOM1 signal 112 by the inverter 24.
The TTRN signal 118, as an output signal of the on-chip compare latch circuit 2, is supplied to one of data-out buffers 8 in FIG. 6, herein a data-out buffer, associated with the compare write data I/0 3, and is read to outside via one of the I/Os 119, herein an I/03.
The circuit operation will now be described by referring to a timing chart of FIG. 9. The respective test modes are activated by the entry of the test mode, mentioned above, to initiate a sequence of operations.
Each inner node point is initialized by a one-shot pulse (HIGH level) of the OCCRST signal 128. The N-channel MOS transistor 19 is turned on so that the signal 135 goes LOW. The output 127 of the NOR circuit 22 goes LOW so that the output of the NOR circuit 21 goes HIGH.
The OCCRST signal 128 goes LOW after initialization with the OCCRST signal 128 being a HIGH-level one-shot pulse. The N-channel MOS transistor 19 is turned off (in the floating state), with the input of the NOR circuit 22 becoming LOW.
The PTEST signal 111 then goes HIGH, whereby the TFF0B signal 117, which is the result of comparison between read data and an expected value externally supplied, is sent via NAND circuit 14 to the signal line 130.
The PDEBL signal 127 goes HIGH to turn on the transistors 17 and 18, so that connection is made to the path which latches and outputs the first LOW level of the TFF0B signal 117.
The signal 135 is LOW in the initial state, so that, when the TFF0B signal 117 becomes LOW, indicating data non-coincidence, the signals 130 and 135 become HIGH, with the output 136 of the NOR circuit 121 going LOW. Since the signal 137 then goes HIGH, the signal 136 of the flip-flop circuit, composed of the NOR circuits 21 and 22, remains fixed at the LOW level, irrespective of the information of the TFF0B signal 117.
After termination of a sequence of internal latch test operations, the TCOM1 signal 112 becomes HIGH by the test mode. The transfer gate (27, 28) is turned on, and the signal 132 becomes the result of the signal 136 which has latched the initial LOW level information of the TFF0B signal 117. The TTRN signal 118 is set to the LOW level.
With the OCOUTB signal 129 then going LOW, the result of the signal 132 is output to the TTRN signal line 118 via inverter 29, NAND 30 and inverter 31.
In case of data non-coincidence, the TTRN signal 118 is HIGH. The data of this TTRN signal 118 is read out to outside from one of the I/Os 119, for example, I/O 3, via data-out buffer 8.
The circuit operation for the path for outputting the data which has latched the initial fail information on the TFF0B signal line 117 has been described in the foregoing. The circuit operation for the other path for directly outputting the data of the TFF0B signal line 117 is simply that, if the TCMP1 signal 112 is LOW, the transfer gates 25, 26 is in the on-state, and hence the data of the signal 130 becomes the signal 131 via inverter 15, while becoming the signal 132 via transfer gate 25, 26, and becoming the signal 133 via inverter 29.
Since the TCMP1 signal 112 is LOW, the output 140 of the NAND circuit 23 becomes HIGH. The data on the signal line 133 becomes the signal 134 via NAND circuit 30, and further becomes the TTRN signal 118 via inverter 31. Thus, in the path under consideration, the TTRN signal 118 becomes an output of the bit-by-bit internal non-coincidence fail information. It is noted that the signal level becomes HIGH in case of non-coincidence.
As for the on-chip comparison test, reference may be made to the following Patent Documents 2 to 4.
[Patent Document 1] JP Patent Kokai Publication No. JP-P2004-303354A
[Patent Document 2] JP Patent Kokai Publication No. JP-P2004-39123A
[Patent Document 3] JP Patent Kokai Publication No. JP-P2003-257194A
[Patent Document 4] JP Patent Kokai Publication No. JP-A-9-128998